1. Field of the Invention
The present invention relates to an information processing device provided in a processor to store an address into address queue register files and read the address therefrom on a FIFO basis to provide it to a main memory control circuit when a cache miss has occurred.
2. Description of the Related Art
FIG. 10 is a schematic block diagram showing a processor of the prior art connected to a main memory.
In the processor 10, an instruction execution circuit 11 calculates an address of an operand included in an instruction, and, if the address is a logical address, further converts it to a corresponding physical address, and then provides it as an address AD to a data access circuit 12.
As shown in FIG. 11, in connection with a cache memory 17, the address AD is divided into fields of a tag TAG, an entry ENT, and an offset OFS in descending order, where the entry ENT is provided to an address input of a tag table 14. A hit/miss determination circuit 15 compares the value of the tag TAG of the input address AD with the value of a tag read from the tag table 14, and provides the compared result, as a cache hit/miss signal H/M, to a cache control circuit 16 of FIG. 10.
The instruction execution circuit 11 provides a request signal RQ to the cache control circuit 16, simultaneously with the provision of the input address AD. In response to the request signal RQ, the cache control circuit 16 provides an acknowledge signal ACK to the instruction execution circuit 11. When the cache hit/miss signal H/M is active, i.e., when a cache hit occurs, the cache control circuit 16 provides the values of the entry ENT and the offset OFS of the input address AD, together with the request signal, to the cache memory 17.
In response to this, the cache memory 17 outputs a part of a long word addressed by the value of the entry ENT to a data output, in which the part of the long word is designated by the value of the offset OFS, and also provides a ready signal to the cache control circuit 16. In response to this, the cache control circuit 16 allows a selector 18 to switch to the output of the cache memory 17, and provide this output, as a read data RD, to the instruction execution circuit 11. At the same time, the cache control circuit 16 provides the ready signal RDY and the input address AD corresponding to the read data RD to the instruction execution circuit 11. In response to this, the instruction execution circuit 11 receives the read data RD as the content of the input address AD.
When the cache hit/miss signal H/M is inactive, i.e., when a cache miss occurs, an address queue control circuit 19 stores the input address AD in a register file 21 of an address queue storing & selecting circuit 20 on a FIFO basis. The address queue control circuit 19 writes a wait state WS, in correspondence with the input address AD, to the register file 21 on a FIFO basis. The wait state WS represents a main memory request wait or the completion of writing a read data from the main memory to the cache memory 17. While providing a main memory read request signal MRQ to the main memory control circuit 23, the address queue control circuit 19 provides a selection control signal to the selector 22 so that the wait state WS and the input address AD stored in the resister file 21 on a FIFO basis (referred to as a “stored input address AD”) are provided to the main memory control circuit 23.
In response to the main memory read request signal MRQ, the main memory control circuit 23 performs the following processes if the wait state WS represents the memory request wait. Namely, the control circuit 23 reads from the main memory 30 a series of data represented by a tag TAG and an entry ENT of a main memory read address MRA corresponding to the stored input address AD read from the register file 21. The control circuit 23 provides the series of data, as a cache write data CD, to the cache memory 17, while providing the main memory read address MRA to the cache control circuit 16. When an address of the cache write data CD currently being output is coincident with the main memory read request signal MRQ, the control circuit 23 provides a ready signal RDY to the cache control circuit 16.
The cache control circuit 16 addresses the cache memory 17 by the tag TAG and the entry ENT of the main memory read address MRA so as to write the cache write data CD to the cache memory 17. In response to the ready signal RDY, the cache control circuit 16 allows the selector 18 to switch to the data CD and provide the corresponding data, as a read data RD, to the instruction execution circuit 11, while providing the read address RA (=MRQ) and the ready signal RDY to the instruction execution circuit 11. When the writing of the data CD to the cache memory 17 is completed, the cache control circuit 16 addresses the tag table 14 by the entry ENT of the main memory read address MRA corresponding to the data CD, so as to write the tag TAG of the address MRA to the tag table 14.
In the case where a plurality of addresses, whose tag TAG and entry ENT are identical to each other, are included in addresses stored in the register file 21, if one of the plurality of addresses is provided to the main memory control circuit 23 to access the main memory 30, it is not necessary to access the main memory 30 for the remaining addresses of the plurality of addresses, and thus the address queue control circuit 19 replaces the current value of the wait state WS in the register file 21 with a value representing the completion of writing to the cache memory 17.
In the case where the wait sate WS represents the writing completion, in response to the main memory read request signal MRQ from the address queue control circuit 19, the main memory control circuit 23 provides the main memory read address MRA and a signal representing the wait state WS to the cache control circuit 16. In response to this, the cache control circuit 16 performs the same process as in the case where the cache hit/miss signal H/M is active.
For the sake of simplification, FIG. 10 omits the illustration of elements in the data access circuit 12 for writing data to the address AD.
Now, a description will be given of the operation of the register file 21, referring to FIG. 12.
For the sake of a simpler explanation, it is assumed that the register file 21 can store up to 3 of the number of the input addresses AD. It is also assumed that any of addresses AD1 to AD4 is an input address of the same tag and entry which causes a cache miss, whereas an address AD5 is an input address which causes a cache hit.
At time T1, the input address AD1 is stored in the register file 21, and it is selected by the selector 22 to be provided to the main memory control circuit 23. A symbol τ is defined to represent the time required for the main memory control circuit 23 to read a series of data from the main memory 30 and store it in the cache memory 17 after gaining read access to the main memory 30.
At times T2 and T3, the input addresses AD2 and AD3 are stored in the register file 21, respectively. The address queue control circuit 19 provides a signal representing a full state of the register file 21 to the cache control circuit 16. In response to this, the cache control circuit 16 causes a busy signal BSY, which is to be provided to the instruction execution circuit 11, to be active. The instruction execution circuit 11 stops the operation until the busy signal BSY is inactive.
For this reason, despite the existence of data of the input address AD5 in the cache memory 17, it is impossible to perform the reading of this data.
At time T1+τ, the stored input address AD1 becomes invalid, and the input address AD4 is stored at the location where the input address AD1 has been stored.
In general, the possibility of using data of addresses in proximity to each other is relatively high, so if an input address AD causes a cache miss, subsequent input addresses having the same tag and entry as the input address AD continuously cause a cache miss. Thereby, the register file 21 becomes full, stopping the operation of the instruction execution circuit 11. This makes it difficult to achieve a higher operating speed.
This problem can be overcome by increasing the storage capacity of the register file 21.
However, this increase the circuit size of the address queue storing & selecting circuit 20, since the input address AD is relatively long, for example, 32 bits.